https://github.com/tilk/riscv-simple-sv

A simple RISC V core for teaching
https://github.com/tilk/riscv-simple-sv

risc-v riscv verilog

Last synced: about 1 month ago
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A simple RISC V core for teaching

• Host: GitHub
• URL: https://github.com/tilk/riscv-simple-sv
• Owner: tilk
• License: bsd-3-clause
• Created: 2019-04-18T13:11:10.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2021-12-30T13:02:50.000Z (almost 3 years ago)
• Last Synced: 2024-08-03T01:39:30.651Z (5 months ago)
• Topics: risc-v, riscv, verilog
• Language: SystemVerilog
• Size: 149 KB
• Stars: 162
• Watchers: 3
• Forks: 18
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# riscv-simple-sv

This is a collection of simple RISC V (rv32i) cores for teaching purposes. They are written in a subset of SystemVerilog understood by [Yosys](http://www.clifford.at/yosys/), the open-source hardware synthesis framework, and [Verilator](https://www.veripool.org/wiki/verilator), an open-source Verilog to C++ compiler. The implementation is extremely simple, no bells and whistles, and it's modularized sensibly, so that schematics generated by synthesis tools are readable.

Three cores are currently implemented:

- single-cycle core (one instruction per cycle, separate instruction and data bus),

- multicycle core (multiple cycles per instruction, single memory bus, only one adder),

- pipelined core (five-stage pipeline).

The single-cycle core is adapted from [riscv-simple](https://github.com/arthurbeggs/riscv-simple). Code structure has been modified for readability, and several bugs have been fixed.

## Testing 

The cores are tested using [official unit tests](https://github.com/riscv/riscv-tests).