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https://github.com/tommythorn/ncl-examples
A collection of Null Convention Logic examples, simulated and synthesized for FPGA
https://github.com/tommythorn/ncl-examples
Last synced: about 5 hours ago
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A collection of Null Convention Logic examples, simulated and synthesized for FPGA
- Host: GitHub
- URL: https://github.com/tommythorn/ncl-examples
- Owner: tommythorn
- License: apache-2.0
- Created: 2023-08-20T04:37:08.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2023-09-09T05:32:47.000Z (over 1 year ago)
- Last Synced: 2025-01-11T16:16:17.674Z (5 days ago)
- Language: Verilog
- Size: 25.4 KB
- Stars: 3
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# NCL-examples
A collection of Null Convention Logic examples, simulated and synthesized for FPGA
The ring.v example is Figure 3.11 "A three-cycle ring" from LDS [1, 2],
generalized to N cycles.
N=4 oscillates at ~ 600 MHz on my Lattice ECP5-85F
## References
[1] Karl Fant's book "Logically Determined Design"
https://www.amazon.com/Logically-Determined-Design-Clockless-Convention-ebook/dp/B000YH90SC
[2] https://www.karlfant.net/