https://github.com/tommythorn/tt07-memory

A very crazy attempt at creating memory from a22o gates (smaller than latches)
https://github.com/tommythorn/tt07-memory

Last synced: about 2 months ago
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A very crazy attempt at creating memory from a22o gates (smaller than latches)

• Host: GitHub
• URL: https://github.com/tommythorn/tt07-memory
• Owner: tommythorn
• License: apache-2.0
• Created: 2024-06-01T01:05:41.000Z (11 months ago)
• Default Branch: main
• Last Pushed: 2024-07-29T21:42:19.000Z (9 months ago)
• Last Synced: 2025-02-24T07:13:52.669Z (2 months ago)
• Language: Verilog
• Homepage:
• Size: 42 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)

# Even tinier RAM

The Sky130 latch cell

![sky130_fd_sc_hd__dlxtp](https://skywater-pdk.readthedocs.io/en/main/_images/sky130_fd_sc_hd__dlxtp_1.svg)

(pitch 12) is larger than the A22O cell

![sky130_fd_sc_hd__a22o_1](https://skywater-pdk.readthedocs.io/en/main/_images/sky130_fd_sc_hd__a22o_1.svg)

(pitch 7) which is all you need to hold state.  Will this matter enough to

create a denser RAM?  That's what this is trying to figure out.

Credit to Mike Bell whose project I have cloned and modified.  All

bugs are mine.

# Tiny Tapeout Verilog Project Template

- [Read the documentation for project](docs/info.md)

## What is Tiny Tapeout?

Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

## Set up your Verilog project

1. Add your Verilog files to the `src` folder.

2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).

3. Edit [docs/info.md](docs/info.md) and add a description of your project.

4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information.

The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).

## Enable GitHub actions to build the results page

- [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part)

## Resources

- [FAQ](https://tinytapeout.com/faq/)

- [Digital design lessons](https://tinytapeout.com/digital_design/)

- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/)

- [Join the community](https://tinytapeout.com/discord)

- [Build your design locally](https://docs.google.com/document/d/1aUUZ1jthRpg4QURIIyzlOaPWlmQzr-jBn3wZipVUPt4)

## What next?

- [Submit your design to the next shuttle](https://app.tinytapeout.com/).

- Edit [this README](README.md) and explain your design, how it works, and how to test it.

- Share your project on your social network of choice:

  - LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [@TinyTapeout](https://www.linkedin.com/company/100708654/)

  - Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn)

  - X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@tinytapeout](https://twitter.com/tinytapeout)