https://github.com/trivialmips/TrivialMIPS

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
https://github.com/trivialmips/TrivialMIPS

cpu fpga fpga-soc mips systemverilog xilinx

Last synced: about 1 month ago
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MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

• Host: GitHub
• URL: https://github.com/trivialmips/TrivialMIPS
• Owner: trivialmips
• Created: 2018-07-16T04:57:40.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2019-04-29T20:59:33.000Z (over 5 years ago)
• Last Synced: 2024-08-03T01:39:31.696Z (5 months ago)
• Topics: cpu, fpga, fpga-soc, mips, systemverilog, xilinx
• Language: SystemVerilog
• Homepage:
• Size: 84.3 MB
• Stars: 102
• Watchers: 10
• Forks: 32
• Open Issues: 0
• Metadata Files:

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