https://github.com/trivialmips/TrivialMIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
https://github.com/trivialmips/TrivialMIPS
cpu fpga fpga-soc mips systemverilog xilinx
Last synced: about 1 year ago
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MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
- Host: GitHub
- URL: https://github.com/trivialmips/TrivialMIPS
- Owner: trivialmips
- Created: 2018-07-16T04:57:40.000Z (almost 8 years ago)
- Default Branch: master
- Last Pushed: 2019-04-29T20:59:33.000Z (about 7 years ago)
- Last Synced: 2024-08-03T01:39:31.696Z (almost 2 years ago)
- Topics: cpu, fpga, fpga-soc, mips, systemverilog, xilinx
- Language: SystemVerilog
- Homepage:
- Size: 84.3 MB
- Stars: 102
- Watchers: 10
- Forks: 32
- Open Issues: 0
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Metadata Files: