https://github.com/tum-ei-eda/coreperfdsl-examples
Examples of CorePerfDSL descriptions
https://github.com/tum-ei-eda/coreperfdsl-examples
Last synced: 2 months ago
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Examples of CorePerfDSL descriptions
- Host: GitHub
- URL: https://github.com/tum-ei-eda/coreperfdsl-examples
- Owner: tum-ei-eda
- License: apache-2.0
- Created: 2024-12-05T14:31:19.000Z (11 months ago)
- Default Branch: main
- Last Pushed: 2025-08-28T11:04:47.000Z (2 months ago)
- Last Synced: 2025-08-28T18:25:29.432Z (2 months ago)
- Size: 36.1 KB
- Stars: 0
- Watchers: 1
- Forks: 2
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# CorePerfDSL-Examples
Examples of CorePerfDSL descriptions
## Models
### CV32E40P
Model of the 4-stage RISC-V CPU CV32E40P.
- Modelled instructions: RV32IM
- Static branch prediction
- No memory model
### CVA6
Model of the 6-stage RISC-V CPU CVA6.
- Modelled instructions: RV64IM
- Instructions queue (IQ) and execute stage with scoreboard
- Dual-commit
- Dynamic branch prediction
- Memory model with internal L1 instructiona and data caches
### SimpleRISCV
Custom example to illustrate flexiblity of CorePerDSL.
- 5-stage, Harvard microarchitecture
- Modelled instructions: RV32IMC
- No, static and dynamic branch prediction
- With and without data forwarding
- Dummy memory model
## Version
This is version v2.0.
This repository does not contain any submodules.