https://github.com/tum-ei-eda/etiss_arch_riscv
RISC-V architecture models for ETISS
https://github.com/tum-ei-eda/etiss_arch_riscv
Last synced: about 2 months ago
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RISC-V architecture models for ETISS
- Host: GitHub
- URL: https://github.com/tum-ei-eda/etiss_arch_riscv
- Owner: tum-ei-eda
- Created: 2022-01-26T22:02:19.000Z (almost 4 years ago)
- Default Branch: master
- Last Pushed: 2025-08-26T08:37:42.000Z (2 months ago)
- Last Synced: 2025-08-26T10:40:45.893Z (2 months ago)
- Size: 68.4 KB
- Stars: 0
- Watchers: 2
- Forks: 10
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# etiss_arch_riscv
This repository contains the top-level CoreDSL 2 files for the RISC-V ISA, customized for use in ETISS. `top.core_desc` contains all core instantiations, `TUM_exc.core_desc` contains various ETISS-specific overrides. The base ISA files are pulled in via a submodule.