https://github.com/tum-ei-eda/m2-isa-r
CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator
https://github.com/tum-ei-eda/m2-isa-r
Last synced: 2 months ago
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CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator
- Host: GitHub
- URL: https://github.com/tum-ei-eda/m2-isa-r
- Owner: tum-ei-eda
- License: apache-2.0
- Created: 2021-07-08T07:51:38.000Z (over 4 years ago)
- Default Branch: coredsl2
- Last Pushed: 2025-07-04T16:52:56.000Z (4 months ago)
- Last Synced: 2025-07-04T17:36:02.198Z (4 months ago)
- Language: Python
- Homepage: https://tum-ei-eda.github.io/M2-ISA-R/
- Size: 1.53 MB
- Stars: 7
- Watchers: 4
- Forks: 7
- Open Issues: 20
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# M2-ISA-R v2
This tool serves as a general-purpose instruction set architecture metamodel. A parser for [CoreDSL](https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual) and an architecture generator for the instruction set simulator [ETISS](https://github.com/tum-ei-eda/etiss) are currently also provided.
**Please note:** M2-ISA-R is in heavy development, things might change and break without notice. Please report issues on GitHub for any problems you encounter.
## Prerequisites
- Python 3.7+ with at least `pip` and `venv`
## Installation (Usage with CoreDSL 2 and ETISS)
- Make a Python `venv` somewhere: `python -m venv `
- Activate said `venv`: `source /bin/activate`
- Install M2-ISA-R: `pip install git+https://github.com/tum-ei-eda/M2-ISA-R@coredsl2`
## Development Setup
- Clone the repository, change into the cloned directory
- Make a Python `venv`: `python -m venv venv`
- Activate said `venv`: `source venv/bin/activate`
- Install M2-ISA-R for development: `pip install -e .`
## Architecture
M2-ISA-R consists of 3 components, two of which are exchangeable for different needs:
Frontend -> Metamodel -> Backend
The frontend transforms a model specification into M2-ISA-R's internal architecture model. This model can then be transformed again to an output format, e.g. models for an ISS. This repo provides a CoreDSL frontend and an ETISS backend.
## Usage
M2-ISA-R v2 currently ships three usable tools: Two parsers (for transforming CoreDSL 1.5 / 2 to a M2-ISA-R metamodel) and a writer (for generating ETISS architecture plugins). These are described seperately in their respective directories, TL;DR version:
- To parse a CoreDSL 2 description: `coredsl2_parser path/to/input/.core_desc`
- To generate ETISS Architecture: `etiss_writer -s path/to/input/gen_model/.m2isarmodel`
For parsers, see [m2isar/frontends/coredsl](m2isar/frontends/coredsl) or [m2isar/frontends/coredsl2](m2isar/frontends/coredsl2). For the ETISS architecture writer, see [m2isar/backends/etiss](m2isar/backends/etiss).
## Roadmap
- [X] CoreDSL 2 support (WIP, RISC-V models are buildable)
- [ ] Formal metamodel description
- [ ] Support for extended CoreDSL 2 features:
- [ ] Loops (WIP, for loops unimplemented)
- [ ] Complex data types
- [ ] Bit-wise aliasing
- [ ] Spawn blocks
- [X] Detection and evaluation of generation-time static expressions
- [X] Better support for translation-time static expressions, see #5 and #6
- [ ] Full generation of ETISS architecture models:
- [ ] Variable width instruction decoding
- [X] Exception handling
- [X] Privilege levels
- [X] Interrupts