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https://github.com/tuna-f1sh/wooden-bits-fpga
Attempt to learn Verilog by porting my binary clock 'Wooden Bits' to Verilog and a Lattice chip.
https://github.com/tuna-f1sh/wooden-bits-fpga
binary clock digit icestorm
Last synced: about 1 month ago
JSON representation
Attempt to learn Verilog by porting my binary clock 'Wooden Bits' to Verilog and a Lattice chip.
- Host: GitHub
- URL: https://github.com/tuna-f1sh/wooden-bits-fpga
- Owner: tuna-f1sh
- License: gpl-3.0
- Created: 2018-12-03T08:23:35.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2018-12-25T09:27:59.000Z (about 6 years ago)
- Last Synced: 2024-10-15T10:18:41.004Z (3 months ago)
- Topics: binary, clock, digit, icestorm
- Language: Verilog
- Size: 4.04 MB
- Stars: 0
- Watchers: 3
- Forks: 0
- Open Issues: 0