https://github.com/tvlad1234/violet
Virtual I/O for FPGAs
https://github.com/tvlad1234/violet
button colorlight ecp5 fpga fpga-board led nextpnr p5js uart verilog-hdl virtual-io-device webserial yosys
Last synced: 2 months ago
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Virtual I/O for FPGAs
- Host: GitHub
- URL: https://github.com/tvlad1234/violet
- Owner: tvlad1234
- Created: 2025-02-22T11:48:27.000Z (3 months ago)
- Default Branch: main
- Last Pushed: 2025-02-22T11:51:20.000Z (3 months ago)
- Last Synced: 2025-02-22T12:28:37.166Z (3 months ago)
- Topics: button, colorlight, ecp5, fpga, fpga-board, led, nextpnr, p5js, uart, verilog-hdl, virtual-io-device, webserial, yosys
- Language: Verilog
- Homepage:
- Size: 0 Bytes
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# violet
Virtual I/O for FPGAs
## What it does
This project enables FPGA designs to use virtual LED, hexadecimal display and button I/O through a web interface, over WebSerial and UART.
## How to use
### User interface
The UI can be launched by opening the [web/index.html](web/index.html) using a web browser which supports WebSerial (Chrome or Edge work). Pressing the "Connect" button in the top-left corner opens the port selector.
### Instantiating Violet in your Verilog design
This repository provides an [example](colorlight_example/top/top_violet_example.v) for the Colorlight 5A-75B V8.2 board, synthesized using Yosys and nextpnr.
To use Violet in your own project, you must include all of the files in the [violet](violet) folder into your design, and instantiate the Violet module as shown in the [example](colorlight_example/top/top_violet_example.v).
## Credits
The UI makes use of the [DSEG](https://github.com/keshikan/DSEG) font by [keshikan](https://github.com/keshikan), [p5.js](https://p5js.org) and [p5.webserial](https://github.com/gohai/p5.webserial) by [Gottfried Haider](https://github.com/gohai).