https://github.com/ucb-bar/esp-opcodes
Custom extensions to the RISC-V opcodes for the UCB-BAR ESP project
https://github.com/ucb-bar/esp-opcodes
Last synced: 3 months ago
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Custom extensions to the RISC-V opcodes for the UCB-BAR ESP project
- Host: GitHub
- URL: https://github.com/ucb-bar/esp-opcodes
- Owner: ucb-bar
- License: other
- Created: 2015-03-02T19:25:15.000Z (over 10 years ago)
- Default Branch: master
- Last Pushed: 2020-05-08T17:36:34.000Z (about 5 years ago)
- Last Synced: 2025-01-16T01:15:26.418Z (5 months ago)
- Language: TeX
- Size: 356 KB
- Stars: 1
- Watchers: 14
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
riscv-opcodes
===========================================================================
This repo enumerates standard RISC-V instruction opcodes and control and
status registers. It also contains a script to convert them into several
formats (C, Scala, LaTeX).
This repo is not meant to stand alone; it is a subcomponent of
[riscv-tools](https://github.com/riscv/riscv-tools) and assumes that it
is part of that directory structure.