https://github.com/ucb-bar/shuttle

A Rocket-based RISC-V superscalar in-order core
https://github.com/ucb-bar/shuttle

Last synced: about 2 months ago
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A Rocket-based RISC-V superscalar in-order core

• Host: GitHub
• URL: https://github.com/ucb-bar/shuttle
• Owner: ucb-bar
• Created: 2023-05-17T02:30:07.000Z (about 2 years ago)
• Default Branch: master
• Last Pushed: 2025-04-03T21:47:10.000Z (about 2 months ago)
• Last Synced: 2025-04-03T22:32:22.112Z (about 2 months ago)
• Language: Scala
• Homepage:
• Size: 271 KB
• Stars: 31
• Watchers: 16
• Forks: 5
• Open Issues: 1
• Metadata Files:
  • Readme: README.md

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README

        
Shuttle: A Rocket-based Superscalar In-order RISC-V Core

========================================================

Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base RV64IMAFDCB instruction set with supervisor and user-mode.

Shuttle is a 7-stage core that can be configured to be dual, three, or quad-issue, although dual-issue is the most sensible design point.

Shuttle is *not* designed to meet any power, performance, or area targets.

It exists purely as a demonstrative example of another RISC-V CPU design point.

The superscalar microarchitecture presents the most advantages for 

 1) floating-point kernels 

 2) RoCC accelerator kernels

 3) vector kernels

 as scalar control code can execute concurrently with floating-point/RoCC/vector instructions, maintaining high utilization of those units.

Shuttle is tape-out proven, and has similar physical design complexity as Rocket.

## Versioning

Only the latest version will be maintained.

* **1.0**: Initial 6-stage RV64GC Release

* **1.1**: Support integration with vector units

* **1.2**: Support B-extension (Zba/Zbb/Zbs)

* **2.0**: 7-stage pipeline