https://github.com/ucb-bar/stac-top

The SRAM timing analysis chip for verifying SRAMs generated by SRAM22
https://github.com/ucb-bar/stac-top

Last synced: 2 months ago
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The SRAM timing analysis chip for verifying SRAMs generated by SRAM22

• Host: GitHub
• URL: https://github.com/ucb-bar/stac-top
• Owner: ucb-bar
• License: bsd-3-clause
• Created: 2023-05-25T05:28:48.000Z (about 2 years ago)
• Default Branch: stac-master
• Last Pushed: 2024-11-18T07:38:39.000Z (7 months ago)
• Last Synced: 2025-03-27T00:22:22.618Z (3 months ago)
• Language: Scala
• Homepage:
• Size: 10.6 MB
• Stars: 5
• Watchers: 11
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • Contributing: CONTRIBUTING.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# SRAM22 Timing Analysis Chip - Chipyard repo

Toplevel for the STAC tapeout, based on [Chipyard](https://github.com/ucb-bar/chipyard)

[STACv1 chip docs](docs/test_chip.md)

[STACv2 chip docs](docs/test_chip2.md)

First-time setup:

- Source Conda install / base environment

- `bsub -Is scripts/build-setup.sh -s 4 -s 6 -s 7 -s 8 -s 9 -f`

- `source ./env.sh`

- `scripts/init-vlsi.sh sky130` (add `openroad` if you don't have access to hammer-mentor-plugins)