https://github.com/ultraembedded/core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs
https://github.com/ultraembedded/core_ddr3_controller

Last synced: about 19 hours ago
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A DDR3 memory controller in Verilog for various FPGAs

• Host: GitHub
• URL: https://github.com/ultraembedded/core_ddr3_controller
• Owner: ultraembedded
• Created: 2020-07-14T22:30:42.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2021-10-10T16:10:37.000Z (about 3 years ago)
• Last Synced: 2024-08-02T09:27:28.153Z (3 months ago)
• Language: Verilog
• Size: 232 KB
• Stars: 328
• Watchers: 18
• Forks: 78
• Open Issues: 2

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