https://github.com/ultraembedded/core_sdram_axi4

SDRAM controller with AXI4 interface
https://github.com/ultraembedded/core_sdram_axi4

axi4 fpga sdram-controller verilog

Last synced: 2 months ago
JSON representation

SDRAM controller with AXI4 interface

• Host: GitHub
• URL: https://github.com/ultraembedded/core_sdram_axi4
• Owner: ultraembedded
• License: gpl-3.0
• Created: 2019-08-07T18:50:35.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2019-08-08T19:40:59.000Z (over 5 years ago)
• Last Synced: 2024-05-02T06:17:39.804Z (9 months ago)
• Topics: axi4, fpga, sdram-controller, verilog
• Language: C++
• Size: 43 KB
• Stars: 64
• Watchers: 5
• Forks: 26
• Open Issues: 1

Awesome Lists containing this project