https://github.com/ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
https://github.com/ultraembedded/core_sdram_axi4
axi4 fpga sdram-controller verilog
Last synced: about 1 year ago
JSON representation
SDRAM controller with AXI4 interface
- Host: GitHub
- URL: https://github.com/ultraembedded/core_sdram_axi4
- Owner: ultraembedded
- License: gpl-3.0
- Created: 2019-08-07T18:50:35.000Z (almost 7 years ago)
- Default Branch: master
- Last Pushed: 2019-08-08T19:40:59.000Z (almost 7 years ago)
- Last Synced: 2025-04-07T13:11:12.285Z (about 1 year ago)
- Topics: axi4, fpga, sdram-controller, verilog
- Language: C++
- Size: 43 KB
- Stars: 89
- Watchers: 5
- Forks: 31
- Open Issues: 0