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https://github.com/ultraembedded/riscv-linux-boot
Trivial RISC-V Linux binary bootloader
https://github.com/ultraembedded/riscv-linux-boot
atomics bootloader bootstrap linux-kernel opensbi opensbi-qemu-linux risc-v riscv-linux rv32im uart
Last synced: about 2 months ago
JSON representation
Trivial RISC-V Linux binary bootloader
- Host: GitHub
- URL: https://github.com/ultraembedded/riscv-linux-boot
- Owner: ultraembedded
- License: mit
- Created: 2019-03-26T22:10:21.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2021-04-03T17:45:59.000Z (over 3 years ago)
- Last Synced: 2024-05-02T06:17:40.460Z (8 months ago)
- Topics: atomics, bootloader, bootstrap, linux-kernel, opensbi, opensbi-qemu-linux, risc-v, riscv-linux, rv32im, uart
- Language: C
- Size: 19.5 KB
- Stars: 39
- Watchers: 6
- Forks: 10
- Open Issues: 0