https://github.com/umarcor/osvb
Open Source Verification Bundle for VHDL and System Verilog
https://github.com/umarcor/osvb
Last synced: about 1 month ago
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Open Source Verification Bundle for VHDL and System Verilog
- Host: GitHub
- URL: https://github.com/umarcor/osvb
- Owner: umarcor
- License: apache-2.0
- Created: 2020-09-26T04:05:57.000Z (over 4 years ago)
- Default Branch: main
- Last Pushed: 2024-01-12T01:13:53.000Z (over 1 year ago)
- Last Synced: 2025-04-12T06:25:27.751Z (about 1 month ago)
- Language: Python
- Homepage: https://umarcor.github.io/osvb
- Size: 1.21 MB
- Stars: 45
- Watchers: 4
- Forks: 7
- Open Issues: 1
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Metadata Files:
- Readme: README.md
- License: LICENSE
- Citation: CITATION.cff
Awesome Lists containing this project
README
## Frameworks and methodologies
- [Coroutine Co-simulation Test Bench (cocotb)](https://hdl.github.io/awesome/items/cocotb)
- [Open Source VHDL Verification Methodology (OSVVM)](https://hdl.github.io/awesome/items/osvvm)
- [SVUnit](https://hdl.github.io/awesome/items/svunit)
- [Universal VHDL Verification Methodology (UVVM)](https://hdl.github.io/awesome/items/uvvm)
- [VUnit](https://hdl.github.io/awesome/items/vunit)
## Simulators/compilers
- [GHDL](https://hdl.github.io/awesome/items/ghdl)
- [Icarus Verilog (iverilog)](https://hdl.github.io/awesome/items/iverilog)
- [Verilator](https://hdl.github.io/awesome/items/verilator)
- [Yosys/CXXRTL](https://hdl.github.io/awesome/items/yosys)
## Proofs of concept
### pyCAPI
### Open Source VHDL Design Explorer (OSVDE)
