https://github.com/vasilescur/computer

Custom ISA computer designed in Logisim and then rewritten in Verilog
https://github.com/vasilescur/computer

Last synced: 3 months ago
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Custom ISA computer designed in Logisim and then rewritten in Verilog

• Host: GitHub
• URL: https://github.com/vasilescur/computer
• Owner: vasilescur
• Created: 2019-01-30T17:05:26.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2019-02-25T16:06:07.000Z (about 6 years ago)
• Last Synced: 2025-01-16T17:34:24.668Z (4 months ago)
• Language: Verilog
• Homepage:
• Size: 81.1 KB
• Stars: 0
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Computer

My hardware implementation of a fully-functioning computer with a custom-designed ISA, written in Verilog.

## WIP

Verilog version is work-in-progress.