https://github.com/veriblock/vblake-rtl

vBlake-RTL
https://github.com/veriblock/vblake-rtl

Last synced: 4 months ago
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vBlake-RTL

• Host: GitHub
• URL: https://github.com/veriblock/vblake-rtl
• Owner: VeriBlock
• License: mit
• Created: 2019-05-09T14:25:26.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2021-01-08T15:17:33.000Z (over 5 years ago)
• Last Synced: 2025-07-26T15:53:49.464Z (11 months ago)
• Language: SystemVerilog
• Size: 5.86 KB
• Stars: 5
• Watchers: 2
• Forks: 8
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# vBlake RTL Implementation

This RTL implementation of vBlake in SystemVerilog provides an optimized hashing core. It does not (currently) contain any board-specific UCF/XDC constraints, FPGA<->Host communication, etc.