https://github.com/viktor-prutyanov/fpga-ir

IR receiver with UART interface
https://github.com/viktor-prutyanov/fpga-ir

fpga ir-receiver remote-control verilog

Last synced: 28 days ago
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IR receiver with UART interface

• Host: GitHub
• URL: https://github.com/viktor-prutyanov/fpga-ir
• Owner: viktor-prutyanov
• License: mit
• Created: 2021-02-14T01:43:45.000Z (almost 4 years ago)
• Default Branch: master
• Last Pushed: 2023-01-15T22:40:53.000Z (almost 2 years ago)
• Last Synced: 2024-03-22T00:53:04.214Z (10 months ago)
• Topics: fpga, ir-receiver, remote-control, verilog
• Language: Verilog
• Homepage:
• Size: 9.77 KB
• Stars: 2
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# FPGA IR

This is IR receiver with UART interface for Altera Cyclone IV FPGA. It works as a simple IR analyzer.

IR receiver like the following is required:

![image](https://user-images.githubusercontent.com/8286747/212570921-4c1ba69d-35cf-41f5-85b2-869bc610357d.png)

Output is in the pulse/space (+/-) format:

 ```

$ python3 read.py

+ 9000

- 4500

+ 570

- 570

+ 570

- 570

+ 570

......

```