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https://github.com/vincent-g-van/one-time-pad-fpga
64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
https://github.com/vincent-g-van/one-time-pad-fpga
diligent nexys4 one-time-pad otp seven-segment verilog vivado
Last synced: about 1 month ago
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64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
- Host: GitHub
- URL: https://github.com/vincent-g-van/one-time-pad-fpga
- Owner: Vincent-G-Van
- Created: 2017-06-13T19:39:32.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2017-06-21T09:20:43.000Z (over 7 years ago)
- Last Synced: 2024-11-21T23:29:57.852Z (about 2 months ago)
- Topics: diligent, nexys4, one-time-pad, otp, seven-segment, verilog, vivado
- Language: Verilog
- Size: 24.3 MB
- Stars: 1
- Watchers: 1
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# One-Time-Pad-FPGA V1.00 (Completed/Working)
Created by Van. June 2017
64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
8-Bits for each of the 8 Seven-Segment LEDS. (8x8=64)
(Possible future improvements, let user decide desired bit size of msg/key/try, use sixteen-segment LEDs)
-64Bit Suspectible to bruteforce attack.
-Seven-Segment difficult to express range of alphabets due to multiple overlaps
Device Details:
Product Category=General Purpose
Family=Artix-7
Sub-Family=Artix-7
Package=CSG324
Speed Grade=-1
Part=xc7a100tcsg324-1
--------------------Demonstration--------------------
Top Level Architecture/Psuedocode Sketch:
Data Path Architecture Sketch:
ASM Chart Sketch:
Sample Translation Table for In(Alphabet/Space->Decimal->Binary Input)
Space-> 0 ->00000000
A-> 1 -> 00000001
B-> 2 -> 00000010
C-> 3 -> 00000011
...
X-> 24 -> 00011000
Y-> 25 -> 00011001
Z-> 26 -> 00011010
Translation Chart Sketch:
DEMO:
