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https://github.com/viveris/jtag-boundary-scanner

JTAG boundary scan debug & test tool.
https://github.com/viveris/jtag-boundary-scanner

boundary-scan debug jtag jtag-boundary-scan jtag-probe tool

Last synced: 6 months ago
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JTAG boundary scan debug & test tool.

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README

          

![JTAG Boundary Scanner logo](https://raw.githubusercontent.com/viveris/jtag-boundary-scanner/master/docs/logo.png)

# JTAG Boundary Scanner

## JTAG Boundary-scan board debugging/test software

The JTAG Boundary Scanner is a JTAG software tool to debug or test any electronic boards with a JTAG interface.

![JTAG Boundary Scanner software](https://raw.githubusercontent.com/viveris/jtag-boundary-scanner/master/docs/JTAG_Boundary_Scanner.png)

### Main characteristics and features

- Windows version GUI.

- Implemented in C.

- BSDL files support.

- Target IO pins sampling and control mode ( SAMPLE & EXTEST ).

- I2C Bus over JTAG emulation.

- SPI Bus over JTAG emulation.

- MDIO Bus over JTAG emulation.

- Parallel port bus over JTAG emulation.

- JTAG Bus scan and devices auto-detection.

- BSDL files auto-load.

- script support.

- socket interface for remote control.

### Supported Probes

- FTDI FT2232H based JTAG probes support (Olimex ARM-USB_OCD-H, Lattice HW-USBN-2B, Xilinx...).

- JLINK JTAG probes support.
Note : JLinkARM.dll need to be copied into the JTAGBoundaryScanner folder for the JLink probes support.

- Parallel port based JTAG probes support (Altera ByteBlaster, Memec IJC-4, Macgraigor Wiggler).

## License

This project is licensed under the GNU General Public License version 3 - see the [LICENSE](LICENSE) file for details