https://github.com/wannabeog/csn-221-project

Implementation of a 24 bit RISC processor
https://github.com/wannabeog/csn-221-project

pipeline-processor risc-processor verilog

Last synced: 4 months ago
JSON representation

Implementation of a 24 bit RISC processor

• Host: GitHub
• URL: https://github.com/wannabeog/csn-221-project
• Owner: wannabeOG
• License: mit
• Created: 2017-08-19T21:40:54.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2019-11-18T09:46:49.000Z (over 6 years ago)
• Last Synced: 2025-02-23T21:32:15.775Z (over 1 year ago)
• Topics: pipeline-processor, risc-processor, verilog
• Language: Verilog
• Homepage:
• Size: 1.28 MB
• Stars: 6
• Watchers: 4
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project