https://github.com/wargio/rz-riscv

Rizin RISC-V assembler/disassembler generator
https://github.com/wargio/rz-riscv

Last synced: 25 days ago
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Rizin RISC-V assembler/disassembler generator

• Host: GitHub
• URL: https://github.com/wargio/rz-riscv
• Owner: wargio
• Created: 2022-02-08T21:41:31.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-02-08T21:42:58.000Z (almost 3 years ago)
• Last Synced: 2024-12-11T11:47:40.992Z (29 days ago)
• Language: C
• Size: 67.4 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Rizin RISC-V assembler/disassembler generator

License: `LGPL-3-0`

### Usage

```

python generate_riscv_table.py riscv-opcodes/opcodes-*  > riscv_opcodes.json

python generate_riscv_disassembler.py > riscv_decode.c

```