https://github.com/weisrc/nesv

NESystem Verilog
https://github.com/weisrc/nesv

basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly

Last synced: 29 days ago
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NESystem Verilog

• Host: GitHub
• URL: https://github.com/weisrc/nesv
• Owner: weisrc
• License: mit
• Created: 2022-04-10T03:10:51.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2023-01-08T19:47:22.000Z (about 2 years ago)
• Last Synced: 2024-11-05T22:44:53.416Z (3 months ago)
• Topics: basys3, emscripten, emulator, fpga, nes, systemverilog, verilator, verilog, vivado, webassembly
• Language: SystemVerilog
• Homepage:
• Size: 1.11 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# NESystem Verilog

Pseudo-school project for fun.

**This is still work in progress**

## Notes

Efficiency is not the main concern of this project, but rather making the code as beginner friendly as possible by having all the individual legal instructions and addressing modes defined as functions.

CPU is not cycle accurate: implements instructions in the minimal amount of cycles required.

This project will be targeting the Basys3 FPGA (vivado), regular computers (verilator) and the web (emscripten).

This project will interface with MicroSD cards as the storage medium and the keyboard as the controller. 

## License

MIT. Wei