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https://github.com/weisrc/nesv
NESystem Verilog
https://github.com/weisrc/nesv
basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly
Last synced: about 5 hours ago
JSON representation
NESystem Verilog
- Host: GitHub
- URL: https://github.com/weisrc/nesv
- Owner: weisrc
- License: mit
- Created: 2022-04-10T03:10:51.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-01-08T19:47:22.000Z (almost 2 years ago)
- Last Synced: 2024-10-11T20:57:17.343Z (25 days ago)
- Topics: basys3, emscripten, emulator, fpga, nes, systemverilog, verilator, verilog, vivado, webassembly
- Language: SystemVerilog
- Homepage:
- Size: 1.11 MB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0