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https://github.com/willprice/architecture-counter-machine
A Counter Machine to be used on the ModuleSim simulator
https://github.com/willprice/architecture-counter-machine
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A Counter Machine to be used on the ModuleSim simulator
- Host: GitHub
- URL: https://github.com/willprice/architecture-counter-machine
- Owner: willprice
- Created: 2014-02-04T15:34:59.000Z (almost 11 years ago)
- Default Branch: master
- Last Pushed: 2014-02-17T23:35:31.000Z (over 10 years ago)
- Last Synced: 2023-04-23T07:53:59.175Z (over 1 year ago)
- Size: 910 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Counter machine
Implemented in ModuleSim, a simulator for the Bristol-designed build-a-comp modules.
## Instructions
Instructions are 8 bits long. The first 3 most significant bits (MSB) are the
OPCODE which instructs what the machine should do. The next bit stores the
address of a register if that instruction uses register, or otherwise is a zero.
Finally the last 4 least significant bits are used for address where the
instruction requires an address.
### Instruction Table:
| Instruction | OPCODE | Description |
|------------------|-------------------------|-------------|
| INC `r_i` | `000r_i-0000` | Increment register `r_i` |
| DEC `r_i` | `001r_i-0000` | Decrement register `r_i` |
| JNZ `[ADR]` | `0100-a_3a_2a_1a_0` | If `r_0 == 0` then `PC = a_3a_2a_1a_0` |
| STR `r_i, [ADR]` | `100r_i-a_3a_2a_1a_0` | `MEM[ADR] = r_i` |
| LSR `r_i, [ADR]` | `101r_i-a_3a_2a_1a_0` | `r_i = MEM[ADR]` |
## Setup
### Decoder
* Shifts are used to get `xCBx` to `xxCB` from the opcode `DCBA`, this is used
to control the first stage of MUX decoding.
* LSH: `0001`, shift up by one to remove `D` giving `CBA0`
* RSH: `0010`, shift down by two to get `00CB`
#### Input MUX to Central AU
* Lower MUX: `0000`: Register 0
* Upper MUX: `0010`: Memory
#### Output DMUX from Central AU
* Lower MUX: `0000`: Register 0
* Upper MUX: `0010`: Memory
### Central AU
* Input B: `0001` (used to increment or decrement registers)
#### AU control
* Lower MUX: `0000`: Add
* Middle MUX: `0110`: Subtract
* Upper MUX: `0001`: Pass through
### Program Counter
* MUX input: `0001`
* Input B: `0001` (used to increment instruction address)
