https://github.com/wojciechmarek/my-fpga-journey
A set of code examples for Tang Nano 1K FPGA board.
https://github.com/wojciechmarek/my-fpga-journey
description-language fpga gowin hardware-description-language logic-circuit logic-gates synthesis tang-nano tang-nano-1k vhdl
Last synced: about 1 month ago
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A set of code examples for Tang Nano 1K FPGA board.
- Host: GitHub
- URL: https://github.com/wojciechmarek/my-fpga-journey
- Owner: wojciechmarek
- Created: 2024-02-10T12:14:39.000Z (about 1 year ago)
- Default Branch: master
- Last Pushed: 2024-09-28T22:47:58.000Z (7 months ago)
- Last Synced: 2025-01-28T14:22:39.313Z (3 months ago)
- Topics: description-language, fpga, gowin, hardware-description-language, logic-circuit, logic-gates, synthesis, tang-nano, tang-nano-1k, vhdl
- Language: VHDL
- Homepage:
- Size: 417 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# My FPGA Journey
This repository is a loose set of all my tries to play with the main FPGA programming languages - VHDL and Verilog.
## Table of Contents
- [AND Gate in VHDL & Verilog](./src/and-gate-in-vhdl-verilog/)
- [Basic blocks](./src/basic-blocks/)
- [Boolean algebra](./src/boolean-algebra/)
- [FPGA Hackaton 2024](./src/fpga-hackaton-2024/)
- [LED Blink](./src/led-blink/)
- [Logic gates](./src/logic-gates/)
- [Test Bench examples](./src/test-bench-examples/)
## Development board
Most of the code is developed to run on [Tang Nano 1K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-1K/Nano-1k.html).
### Hardware overview
- **FPGA Chip**: GW1NZ series (first generation of the LittleBee family)
- **LUT4**: 1152
- **Register**: 864
- **Block SRAM (bits)**: 72K
- **Shadow SRAM (bits)**: 4K
- **User Flash (bits)**: 64K
- **Buttons - 2 user programmable buttons**
- **LED Onboard - 1 programmable RGB LED**
- **Core Voltage (LV)**: 1.2V
- **BankVoltage**: The default 3.3 V
- **Write cycles**: 10000
- **IO ports amperage**: 4mA, 8mA, 16mA, 24mA
- **IO ports features**: Independent bus keeper, pull-up / pull-down resistor and open drain output
- **IO ports interfaces**: FPC - Flexible Printed Circuit
### Board and pinout
## Development software
The Tang Nano 1K comes with free (education) version of it's native IDE - [GOWIN](https://www.gowinsemi.com/en/). It supports both Verilog and VHDL.
## Sources
- [In Polish: Wprowadzenie do opisu sprzętu w układach FPGA z wykorzystaniem języka VHDL](https://sii.pl/blog/wprowadzenie-do-opisu-sprzetu-w-ukladach-fpga-z-wykorzystaniem-jezyka-vhdl/)
- [Tutorial 9: S-R Latch in VHDL](https://startingelectronics.org/software/VHDL-CPLD-course/tut9-SR-latch/)
- [VHDL Tutorials and Examples](https://nandland.com/learn-vhdl/)