https://github.com/wokwi/tiny-tapeout-test-simple

7 Segment GDS fun
https://github.com/wokwi/tiny-tapeout-test-simple

Last synced: 4 months ago
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7 Segment GDS fun

• Host: GitHub
• URL: https://github.com/wokwi/tiny-tapeout-test-simple
• Owner: wokwi
• License: apache-2.0
• Created: 2022-08-09T08:45:02.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-08-09T08:45:47.000Z (almost 3 years ago)
• Last Synced: 2025-01-16T14:51:29.132Z (5 months ago)
• Language: Verilog
• Size: 5.86 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE

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README

        
![](../../workflows/wokwi/badge.svg)

# How to change the Wokwi project

Edit the [Makefile](Makefile) and change the WOKWI_PROJECT_ID to match your project.

# What is this about?

This repo is a template you can make a copy of for your own [ASIC](https://www.zerotoasiccourse.com/terminology/asic/) design using [Wokwi](https://wokwi.com/).

When you edit the Makefile to choose a different ID, the [GitHub Action](.github/workflows/wokwi.yaml) will fetch the digital netlist of your design from Wokwi.

The design gets wrapped in some extra logic that builds a 'scan chain'. This is a way to put lots of designs onto one chip and still have access to them all. You can see [all of the technical details here](https://github.com/mattvenn/scan_wrapper).

After that, the action uses the open source ASIC tool called [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/) to build the files needed to fabricate an ASIC.

# What files get made?

When the action is complete, you can [click here](https://github.com/mattvenn/wokwi-verilog-gds-test/actions) to see the latest build of your design. You need to download the zip file and take a look at the contents:

* gds_render.svg - picture of your ASIC design

* runs/wokwi/reports/final_summary_report.csv  - CSV file with lots of details about the design

* runs/wokwi/reports/synthesis/1-synthesis.stat.rpt.strategy4 - list of the [standard cells](https://www.zerotoasiccourse.com/terminology/standardcell/) used by your design

* runs/wokwi/results/final/gds/user_module.gds - the final [GDS](https://www.zerotoasiccourse.com/terminology/gds2/) file needed to make your design

# What next?

* Share your GDS on twitter and link to us!

* If you want your design to be fabricated, we are aiming to do this for around $100. Let me know if [you're interested in participating](https://docs.google.com/forms/d/1ArnCrpKvf8IC4ouLv_lIwV_8ObRSTTtUYgfZqWvY9-k/edit).