https://github.com/wpmed92/takerisc

A RISC-V RV32I Core written in TL-Verilog
https://github.com/wpmed92/takerisc

hardware riscv riscv32 tl-verilog verilog

Last synced: about 1 month ago
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A RISC-V RV32I Core written in TL-Verilog

• Host: GitHub
• URL: https://github.com/wpmed92/takerisc
• Owner: wpmed92
• Created: 2022-08-26T17:28:45.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2022-08-26T18:01:46.000Z (over 2 years ago)
• Last Synced: 2023-04-24T08:40:36.440Z (over 1 year ago)
• Topics: hardware, riscv, riscv32, tl-verilog, verilog
• Homepage:
• Size: 1.95 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0

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