https://github.com/wvangansbeke/high-level-synthesis

Convert C files into Verilog
https://github.com/wvangansbeke/high-level-synthesis

c-plus-plus high-level-synthesis verilog

Last synced: 2 months ago
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Convert C files into Verilog

• Host: GitHub
• URL: https://github.com/wvangansbeke/high-level-synthesis
• Owner: wvangansbeke
• Created: 2019-01-27T11:44:46.000Z (almost 6 years ago)
• Default Branch: master
• Last Pushed: 2019-01-27T16:47:44.000Z (almost 6 years ago)
• Last Synced: 2023-03-04T23:42:55.694Z (almost 2 years ago)
• Topics: c-plus-plus, high-level-synthesis, verilog
• Language: C++
• Homepage:
• Size: 1.89 MB
• Stars: 12
• Watchers: 3
• Forks: 4
• Open Issues: 0

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