https://github.com/wyvernSemi/pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog
https://github.com/wyvernSemi/pcievhost

bfm c cosim modelling pcie pli verification verilog virtual

Last synced: 3 months ago
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PCIe (1.0a to 2.0) Virtual host model for verilog

• Host: GitHub
• URL: https://github.com/wyvernSemi/pcievhost
• Owner: wyvernSemi
• License: gpl-3.0
• Created: 2016-10-07T14:50:15.000Z (about 8 years ago)
• Default Branch: master
• Last Pushed: 2024-07-27T12:02:48.000Z (3 months ago)
• Last Synced: 2024-07-27T13:25:16.396Z (3 months ago)
• Topics: bfm, c, cosim, modelling, pcie, pli, verification, verilog, virtual
• Language: C
• Homepage: http://www.anita-simulators.org.uk/wyvernsemi
• Size: 3.1 MB
• Stars: 70
• Watchers: 12
• Forks: 18
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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• awesome-opensource-hardware - pcievhost

README

        
# pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog.

Generates PCIe Physical, Data Link and Transaction Layer traffic for up to 16 lanes, controlled from user C program, via an API. Has configurable internal memory and configuration space models, and will auto-generate completions (configurably), with flow control, ACKs, and NAKS etc.

pcievhost is bundled with verilog pcie link traffic display modules and an example test harness. Tested for ModelSim/Questa only at the present time, though easily adpated for VCS, NC-Verilog and Icarus (and has previously been running on these in the past).







More informaton can be found in the documentation doc/pcieVHost.pdf