https://github.com/xigh/verilog-simple-regfile

Simple parameterized registry file written in verilog
https://github.com/xigh/verilog-simple-regfile

Last synced: 3 months ago
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Simple parameterized registry file written in verilog

• Host: GitHub
• URL: https://github.com/xigh/verilog-simple-regfile
• Owner: xigh
• License: bsd-2-clause
• Created: 2018-04-19T06:51:53.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2018-04-19T06:52:38.000Z (about 7 years ago)
• Last Synced: 2025-01-08T06:20:07.819Z (5 months ago)
• Language: Verilog
• Size: 1.95 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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# verilog-simple-regfile

Simple parameterized registry file written in verilog