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Curated list of awesome resources related with RISC-V
https://github.com/xmpf/awesome-risc-v

List: awesome-risc-v

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Curated list of awesome resources related with RISC-V

Awesome Lists containing this project

README 

        
# Curated List of Awesome RISC-V resources



## RISCV.ORG

+ [Software / Tools](https://github.com/riscv/riscv-software-list)  

+ [Educational Material](https://github.com/riscv/educational-materials)  

+ [Implementations](https://riscv.org/risc-v-cores/)  

+ [Unit tests](https://github.com/riscv/riscv-tests)  



## Research Papers

+ [Papers](./papers/)



## Implementations

+ https://github.com/chipsalliance/rocket-chip  

+ https://github.com/riscv-boom/riscv-boom  

+ https://github.com/risclite/SuperScalar-RISCV-CPU  

+ https://github.com/pulp-platform/ariane  

+ https://github.com/ucb-bar/zscale  

+ https://leros-dev.github.io/  

+ https://github.com/t-crest/patmos  

+ https://github.com/schoeberl/lipsi  

+ https://github.com/bu-icsg/dana  

+ https://github.com/ucb-bar/riscv-sodor  

+ https://github.com/mballance/fwrisc  

+ https://github.com/lowRISC/ibex  

+ https://github.com/cliffordwolf/picorv32  

+ https://github.com/olofk/serv  

+ https://github.com/chipsalliance/Cores-SweRV  

+ https://github.com/SpinalHDL/VexRiscv  

+ https://github.com/ucb-bar/riscv-mini  

+ https://gitlab.com/sfu-rcl/Taiga

+ https://github.com/westerndigitalcorporation/swerv_eh1_fpga  

+ https://github.com/PulseRain/Reindeer 

+ https://github.com/PulseRain/Rattlesnake  

### Extensions

+ [RISC-V V vector extension](https://github.com/riscv/riscv-v-spec)  



## Tools

+ https://github.com/ncppd/rocket-chip-tlb-generator  

+ https://github.com/ucb-bar/riscv-torture  

+ https://github.com/mortbopet/Ripes  

+ https://github.com/mickflemm/yarvt  

+ https://github.com/ucb-bar/chipyard  

+ https://github.com/CSL-KU/firesim-nvdla  

+ https://github.com/westerndigitalcorporation/swerv-ISS  

+ [GAP8 SDK](https://github.com/GreenWaves-Technologies/gap_sdk)  

+ https://github.com/olofk/fusesoc  

### Simulators

+ https://github.com/nbdd0121/TLBSim  

+ [FireSim](https://fires.im/)  

### IDE

+ https://www.segger.com/downloads/embedded-studio  

### DSE (Design Space Exploration)

+ [BRISC-V](https://ascslab.org/research/briscv/explorer/explorer.html)  

### Virtual Machine

+ [Virtual Machine for RISC-V development](https://github.com/openhwgroup/riscv_vm/)  



## News

+ https://www.aitrends.com/  

+ https://www.hotchips.org/  

+ https://hub.packtpub.com/

+ https://www.design-reuse.com/

+ https://abopen.com/

+ https://www.cnx-software.com/

+ https://semiengineering.com/ 

+ https://www.openhwgroup.org/#news  

+ [ASCS Lab - Boston University](https://ascslab.org/research.html)  



## Blogs

+ http://libre-riscv.org/

+ https://dantalion.nl/en/risc-v-rv32i-assembly-with-ripes-simulator/

+ https://www.linkedin.com/pulse/2019-year-risc-v-open-source-silicon-olof-kindgren/  



## Forums

+ https://riscv.org/forum/  



## Tutorials . Guides

+ https://riscv.ics.forth.gr/doku.php/developers/getting_started

+ [Lab 1: hackmd@sysprog](https://hackmd.io/@sysprog/H1TpVYMdB)  

+ [Lab 2: hackmd@sysprog](https://hackmd.io/@sysprog/rJAufgHYS)  

+ [Lab 3: hackmd@sysprog](https://hackmd.io/@sysprog/rJw2A5DqS)  

+ [Assignment 1: hackmd@sysprog](https://hackmd.io/@sysprog/By5OE6fOr)

+ [Assignment 2: hackmd@sysprog](https://hackmd.io/@sysprog/rJdsV7Btr)  



## YouTube . Twitch

+ [RISC-V Workshop Zurich 2019](https://www.youtube.com/playlist?list=PL85jopFZCnbMcS3bdzdd7AdLop5DtEOWB)

+ [Looking into Hello World on RISC-V by Dennis Clarke (twitch.tv/lastmiles)](https://www.twitch.tv/tsoding/video/498698691)

## Conferences

+ https://www.osdforum.org/



## Podcasts



## Courses

+ [CS 250: VLSI Systems Design](http://www-inst.eecs.berkeley.edu/~cs250/sp17/)  

+ [Chisel Bootcamp](https://github.com/freechipsproject/chisel-bootcamp)  

+ [EC 413 Computer Organization - Boston](https://ascslab.org/courses/ec413/lectures.html)

### Workshops

+ https://riscv.org/category/workshops/ 

+ [Getting Started with RISC-V: Europe Roadshow Proceedings - September 2019](https://riscv.org/2019/10/getting-started-with-risc-v-europe-roadshow-proceedings/)   



## Books

+ [Chisel Book - Martin Schoeberl](https://github.com/schoeberl/chisel-book)  



## Documentation . Notes

+ https://github.com/cnrv/riscv-notes  

+ https://github.com/Intensivate/learning-journey/wiki/Learning-journey  

### RISC-V Assembly

+ https://github.com/riscv/riscv-asm-manual

### Chisel

+ https://www.chisel-lang.org/api/latest  

+ https://github.com/freechipsproject/chisel3/wiki/Cookbook  

+ https://github.com/IAMAl/How2Start_Chisel3  

+ https://github.com/librecores/riscv-sodor/wiki/Advanced-Examples-of-Using-Chisel  

+ https://github.com/ccelio/chisel-style-guide  

### Scala

+ https://docs.scala-lang.org/style/  

### ChipYard

+ https://chipyard.readthedocs.io/en/latest/  

### RocketChip

+ https://github.com/cnrv/rocket-chip-read  

### BOOM

+ https://github.com/ccelio/riscv-boom-doc  



## Google Groups

+ https://groups.google.com/a/groups.riscv.org/forum/#!forum/hw-dev  

+ https://groups.google.com/a/groups.riscv.org/forum/#!forum/riscv-teach  

+ https://groups.google.com/a/groups.riscv.org/forum/#!forum/isa-dev  

+ https://groups.google.com/forum/#!forum/chisel-users  



## Telegram Channels

+ https://t.me/riscv  



### Uncategorized

+ 

RESOURCES



https://github.com/cnrv/CNRV-FPU  

  

https://github.com/mit-pdos/xv6-riscv-book  

https://github.com/mit-pdos/xv6-riscv  

  

https://github.com/PeterAaser/RISCV-FiveStage  

  

https://github.com/adamwalker/clash-riscv  

  

https://github.com/mrLSD/riscv-fs  

  

https://riscv.ics.forth.gr/doku.php/developers/env_prepare  

Guide toolchain  

  

  

  

https://github.com/westerndigitalcorporation/RISC-V-Linux/  

Linux riscv  

https://www.cl.cam.ac.uk/~pes20/sail/  

Sail, isa semantics, language  

https://github.com/rems-project/sail-riscv  

Sail, riscv, isa  

http://riscv.org.s3-website-us-west-1.amazonaws.com/download.html#tab_rocket  

Rocket  

http://riscv.org.s3-website-us-west-1.amazonaws.com/download.html#tab_rocket  

Linux, riscv  

https://www.ocf.berkeley.edu/~qmn/research.html  

Riscv researcher	  

https://github.com/sifive/last-week-in-risc-v  

RISCV news  

https://github.com/riscv-boom/boom-attacks  

BOOM attacks  

https://github.com/michaeljclark/riscv-attacks  

RISCV attacks  

  

https://github.com/cnrv/rocket-chip-read  

notes  

  

BOOKS / SLIDES / DOCS  

http://events.dvcon.org/Europe/2018/proceedings/slides/07T.pdf  

Design, Verification  

https://raw.githubusercontent.com/wiki/schoeberl/chisel-book/chisel-book.pdf  

Chisel, Digital Design, RISC-V  

https://riscv.org/wp-content/uploads/2015/01/riscv-chisel-tutorial-bootcamp-jan2015.pdf  

Chisel, Accelerating Hardware Design, RISC-V  

  

http://hwacha.org/  

Accelerators  

  

https://ccelio.github.io/riscv-boom-doc/  



RISCV resources  



http://csg.csail.mit.edu/6.375/6_375_2019_www/handouts.html  

Complex Digital Systems  

http://pages.cs.wisc.edu/~karu/courses/cs752/fall2016/wiki/index.php?n=Main.Project  

https://passlab.github.io/CSE564/  

https://github.com/PeterAaser/tdt4255-chisel-intro  

Chisel  

  

NEWS / BLOGS  

https://www.cnx-software.com/2019/08/27/risc-v-bases-and-extensions-explained/  

https://www.youtube.com/playlist?list=PLn__0BqzWEWPIsUE0TUdsspej2vHV-osY  

https://wiki.debian.org/RISC-V  

  

  

SCRIPTS/TOOLS/REPOS  

  

https://github.com/seldridge/rocket-rocc-examples  

  

https://github.com/pretis/flexpret  

  

https://github.com/freechipsproject/chisel-bootcamp  

http://www.opensocfabric.org/home.php  

https://github.com/ucb-bar/berkeley-hardfloat  

https://github.com/ucb-bar/rocc-template  

  

  

Stress test  

https://github.com/ucb-bar/fpga-zynq  

https://github.com/ucb-bar/groundtest  

https://github.com/CTSRD-CHERI/axe  

Memory consistency tester