https://github.com/xujiandong/riscv-naive-assembler

A naive assembler for RISC-V, only some special instructions are supported: B-Extension.
https://github.com/xujiandong/riscv-naive-assembler

Last synced: about 2 months ago
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A naive assembler for RISC-V, only some special instructions are supported: B-Extension.

• Host: GitHub
• URL: https://github.com/xujiandong/riscv-naive-assembler
• Owner: XuJiandong
• License: mit
• Created: 2021-07-01T05:26:18.000Z (over 3 years ago)
• Default Branch: master
• Last Pushed: 2021-07-02T06:19:00.000Z (over 3 years ago)
• Last Synced: 2023-03-23T03:47:02.231Z (almost 2 years ago)
• Language: Rust
• Size: 10.7 KB
• Stars: 0
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# riscv-naive-assembler

A naive assembler for RISC-V, only some special instructions are supported: B-Extension.

# Usage

```text

riscv-naive-assembler --input in.S 

```

or

```text

cat in.S | riscv-naive-assembler

```

It can only convert RISC-V extension instructions into .byte instructions. Other instructions are dumped directly.