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https://github.com/yantavares/risc-v-unicycle
Repository for RISC-V Unicycle Processor Implementation in VHDL and Course Material for 'Organization and Architecture of Computers' at UnB (2023/2)
https://github.com/yantavares/risc-v-unicycle
processor risc-v vhdl
Last synced: about 1 month ago
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Repository for RISC-V Unicycle Processor Implementation in VHDL and Course Material for 'Organization and Architecture of Computers' at UnB (2023/2)
- Host: GitHub
- URL: https://github.com/yantavares/risc-v-unicycle
- Owner: yantavares
- License: gpl-3.0
- Created: 2023-09-21T17:47:08.000Z (over 1 year ago)
- Default Branch: master
- Last Pushed: 2024-01-25T20:32:14.000Z (12 months ago)
- Last Synced: 2024-12-15T18:47:21.420Z (about 1 month ago)
- Topics: processor, risc-v, vhdl
- Language: VHDL
- Homepage:
- Size: 18.5 MB
- Stars: 8
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# OAC [ en ]
[](https://github.com/yantavares/OAC)
[](https://opensource.org/license/gpl-3-0/)
Repository for RISC-V Unicycle Processor Implementation in VHDL and Course Material for 'Organization and Architecture of Computers' at UnB (2023/2)
The course is based on the RISC-V architecture, and the projects are done in Assembly, Python, and VHDL.
**Note:** If this repository helped you, please leave a :star: on the repo :)
## Projects
Detailed explanations of the projects and their implementations can be found in the READMEs of each project's folder (in English).
### Project 1: Implementation of the IDEA algorithm (Assembly)
To simulate Project 1, I recommend using [RARS](https://github.com/TheThirdOne/rars). To install, just download the `.jar` file and execute it with the command `java -jar rars.jar` or by double-clicking the file.
### Project 2 -> Python;
For Project 2, you only need to have Python installed on your machine. To execute the project, just run the `simulator.py` file.
### Project 3, etc. -> VHDL
Starting from Project 3, all were done in VHDL. To simulate the projects, I recommend using [GHDL](https://github.com/ghdl/ghdl) and [GTKWave](http://gtkwave.sourceforge.net/). Installation instructions can be found in their respective repositories.
# OAC [ pt ]
[](https://github.com/yantavares/OAC)
[](https://opensource.org/license/gpl-3-0/)
Repositório destinado à implementação de Processador Uniciclo RISC-V em VHDL e Material do Curso 'Organização e Arquitetura de Computadores' na UnB (2023/2)
A disciplina se baseia na arquitetura RISC-V, e os projetos são feitos em Assembly, Python e VHDL.
**Obs.:** Se esse repositório te ajudou, por favor deixe uma :star: no repo :)
## Projetos
Explicações detalhadas dos projetos e suas implementações podem ser encontradas nos READMEs da pasta de cada projeto (em inglês).
### Projeto 1: Implementação do algoritmo IDEA (Assembly)
Para simular o projeto 1, recomendo o uso do [RARS](https://github.com/TheThirdOne/rars). Para instalar, basta baixar o arquivo `.jar` e executá-lo com o comando `java -jar rars.jar` ou clicando duas vezes no arquivo.
### Projeto 2 -> Python;
Para o projeto 2, é apenas necessário ter o Python e Numpy instalados na máquina.
Você pode instalar o Numpy com o pip:
```bash
pip install numpy
```
ou
```bash
pip3 install numpy
```
Para executar o projeto, basta executar o arquivo `simulador.py`.
### Projeto 3, etc. -> VHDL
A partir do projeto 3, todos foram feitos em VHDL. Para simular os projetos, recomendo o uso do [GHDL](https://github.com/ghdl/ghdl) e do [GTKWave](http://gtkwave.sourceforge.net/). Instruções de instalação podem ser encontradas nos respectivos repositórios.