https://github.com/yasnakateb/aes

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
https://github.com/yasnakateb/aes

aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl

Last synced: 8 months ago
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🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

• Host: GitHub
• URL: https://github.com/yasnakateb/aes
• Owner: yasnakateb
• Created: 2022-02-23T17:04:23.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2022-03-22T15:25:56.000Z (over 3 years ago)
• Last Synced: 2025-01-20T00:56:29.319Z (10 months ago)
• Topics: aes, aes-128, aes-encryption, encryption, encryption-algorithm, icarus-verilog, iverilog, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 32.2 KB
• Stars: 3
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Advanced Encryption Standard

The Advanced Encryption Standard (AES) is a symmetric block cipher to encrypt sensitive data. This implementation supports a 128-bit key. AES-128 bit requires 10 rounds to complete the full operation. The input data is 128 bits and the input key is also 128-bit and each round requires 1 cycle to complete.

## The schematic of AES structure

![](assets/view.jpg)

### Steps

   * Add round key

   

   * Substitute bytes

   

   * Shift rows

   

   * Mix columns

   

## Building on macOS

1. Icarus-Verilog can be installed via Homebrew :

   $ brew install icarus-verilog

2. Download [Scansion](http://www.logicpoet.com/scansion/) from here.  

3. Clone the repository.

4. Run $ make  and type MIPS code to see it in binary form in rams_init_file.hex file. 

5. $ make simulate will: 

* compile design+TB

* simulate the verilog design

6. $ make display will: 

*  display waveforms.