https://github.com/yasnakateb/aes

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
https://github.com/yasnakateb/aes

aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl

Last synced: about 2 months ago
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🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

• Host: GitHub
• URL: https://github.com/yasnakateb/aes
• Owner: yasnakateb
• Created: 2022-02-23T17:04:23.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-03-22T15:25:56.000Z (almost 3 years ago)
• Last Synced: 2023-03-09T08:11:36.368Z (almost 2 years ago)
• Topics: aes, aes-128, aes-encryption, encryption, encryption-algorithm, icarus-verilog, iverilog, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 32.2 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0

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