https://github.com/yasnakateb/fifomemory
📍 A FIFO Memory Implementation in Verilog HDL
https://github.com/yasnakateb/fifomemory
fifo-memory icarus-verilog
Last synced: 4 months ago
JSON representation
📍 A FIFO Memory Implementation in Verilog HDL
- Host: GitHub
- URL: https://github.com/yasnakateb/fifomemory
- Owner: yasnakateb
- Created: 2019-08-16T22:31:50.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2019-09-13T03:08:20.000Z (almost 6 years ago)
- Last Synced: 2025-01-20T00:56:24.131Z (5 months ago)
- Topics: fifo-memory, icarus-verilog
- Language: Verilog
- Homepage:
- Size: 128 KB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# FIFO Memory
A FIFO or Queue is an array of memory to transfer transfer data between two circuits with different clocks. FIFO uses a dual port memory and there will be two pointers to point read and write addresses.[More information](https://www.globalspec.com/learnmore/semiconductors/memory_chips/fifo_memory_chips).
# Behavior
#### Status signals
1. Full: high when FIFO is full.
2. Empty: high when FIFO is empty.
#### Counter
Counter will be incremented if:
* Write takes place and buffer is not full.
Counter will be decremented if:
* Read takes place and buffer is not empty.
🚫🚫🚫 If both read and write takes place, counter will remain the same.
Dependencies
============
## macOS
This project needs [Icarus-Verilog](http://iverilog.icarus.com) and a VCD viewer.
## Building on macOS
1. Icarus-Verilog can be installed via Homebrew :
$ brew install icarus-verilog
2. Download [Scansion](http://www.logicpoet.com/scansion/) from here.
3. Clone the repository.
4. Change the directory to src.
5. $ make simulate will:
* compile design+TB
* simulate the verilog design
6. $ make display will:
* display waveforms.
------
### Block diagram of FIFO
