https://github.com/yasnakateb/multiclocksynchronization

⏰ Fpga Multi Clock Synchronization
https://github.com/yasnakateb/multiclocksynchronization

cdc clock clock-generator clock-management clock-synchronization digital-design fpga hardware-design mmcm multi-clock producer-consumer systemverilog timing-analysis

Last synced: 3 months ago
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⏰ Fpga Multi Clock Synchronization

• Host: GitHub
• URL: https://github.com/yasnakateb/multiclocksynchronization
• Owner: yasnakateb
• License: mit
• Created: 2025-06-24T11:53:45.000Z (11 months ago)
• Default Branch: main
• Last Pushed: 2025-06-24T12:00:45.000Z (11 months ago)
• Last Synced: 2025-10-29T08:25:32.134Z (7 months ago)
• Topics: cdc, clock, clock-generator, clock-management, clock-synchronization, digital-design, fpga, hardware-design, mmcm, multi-clock, producer-consumer, systemverilog, timing-analysis
• Language: SystemVerilog
• Homepage:
• Size: 44.9 KB
• Stars: 0
• Watchers: 0
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# Fpga Multi Clock Synchronization

This project demonstrates **multi-clock domain data synchronization** using **clock domain crossing (CDC)** techniques, including **clock steering**, **MMCM-based clock generation**, and an **asynchronous FIFO** for safe data transfer between different clock domains.

![](assets/system.png)

## Module Breakdown

This design shows how to transfer data from a fast-changing clock domain to a slower one using:

- 🕘 **Multiple Clock Inputs** (150 MHz and 200 MHz)  

- 🧭 **Clock Steering** (select one clock at runtime)  

- 🔁 **Basic Mixed-Mode Clock Manager (MMCM)** to generate internal clocks  

- 📦 **CDC FIFO** (asynchronous FIFO) for safe data transfer across domains  

- 🎯 **Producer-Consumer model** for data movement and monitoring  

## Getting Started

This project is written in SystemVerilog and is intended for use with **Xilinx Vivado**.

1. **Open Vivado** and create a new project.

2. **Add Design Sources**:

   - Add all files from `hdl/src/`:

     - `cdc_fifo.sv`

     - `data_consumer.sv`

     - `data_producer.sv`

     - `mixed_mode_clock_manager.sv`

   - Add `hdl/top.sv` and set it as your **Top Module**.

3. **Add Simulation Sources**:

   - Add `test/tb_top.sv` to the simulation sources.

4. **Run Simulation**:

   - Set `tb_top` as the simulation top module.

   - Run a behavioral simulation to verify functionality.