https://github.com/yasnakateb/nocrouter
👶🏻 My first baby steps into the world of NoC
https://github.com/yasnakateb/nocrouter
icarus-verilog iverilog router verilog verilog-hdl
Last synced: 4 months ago
JSON representation
👶🏻 My first baby steps into the world of NoC
- Host: GitHub
- URL: https://github.com/yasnakateb/nocrouter
- Owner: yasnakateb
- Created: 2021-11-13T14:01:44.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-09-01T15:24:08.000Z (almost 3 years ago)
- Last Synced: 2025-01-20T00:56:24.525Z (5 months ago)
- Topics: icarus-verilog, iverilog, router, verilog, verilog-hdl
- Language: Verilog
- Homepage:
- Size: 269 KB
- Stars: 11
- Watchers: 2
- Forks: 2
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# NoCRouter
Routing is the process of moving a packet of data from source to destination and enables messages
to pass from one computer to another and eventually reach the target machine. A router is a networking device
that forwards data packets between computer networks. It is connected to two or more data lines from different
networks.
## Implementation
In this project, the proposed design of the router includes components like FIFO, register,
synchronizer, FSM and input and output signals between them. The register implements 4 internal registers in order to hold a header byte, FIFO full state byte, internal parity and packet parity byte. The synchronizer provides synchronization between router FSM and router FIFO modules. It provides faithful
communication between the single input port and three output ports.
### States
This router has eight stages:
#### STATE_DECODE_ADDRESS
Next ==> STATE_LOAD_FIRST_DATA (Sig_Packet_Valid = 1, Sig_Fifo_Empty = 1)
Next ==> STATE_WAIT_TILL_EMPTY (Sig_Packet_Valid = 1, Sig_Fifo_Empty = 0)
#### STATE_WAIT_TILL_EMPTY
Next ==> STATE_WAIT_TILL_EMPTY (Sig_Fifo_Empty = 1)
Next ==> STATE_LOAD_FIRST_DATA (Sig_Fifo_Empty = 0)
#### STATE_LOAD_FIRST_DATA
Next ==> STATE_LOAD_DATA
#### STATE_LOAD_DATA
Next ==> STATE_LOAD_PARITY (Sig_Packet_Valid = 0, Sig_Fifo_Full = 0)
Next ==> STATE_FIFO_FULL (Sig_Fifo_Full = 1)
Next ==> STATE_LOAD_DATA
#### STATE_LOAD_PARITY
Next ==> STATE_FIFO_FULL (Sig_Fifo_Full = 1)
Next ==> STATE_CHECK_PARITY_ERROR
#### STATE_FIFO_FULL
Next ==> STATE_FIFO_FULL (Sig_Fifo_Full = 1)
Next ==> STATE_LOAD_AFTER_FULL (Sig_Fifo_Full = 0)
#### STATE_LOAD_AFTER_FULL
Next ==> STATE_LOAD_DATA (Sig_Parity_Done = 0, Sig_Low_Packet_Valid = 0)
Next ==> STATE_LOAD_PARITY (Sig_Parity_Done = 0, Sig_Low_Packet_Valid = 1)
#### STATE_CHECK_PARITY_ERROR
Next ==> STATE_FIFO_FULL (Sig_Fifo_Full = 1)
Next ==> STATE_DECODE_ADDRESS (Sig_Fifo_Full = 0)
## Dependencies
### macOS
This project needs [Icarus-Verilog](http://iverilog.icarus.com) and a VCD viewer.
## Building on macOS
1. Icarus-Verilog can be installed via Homebrew :
$ brew install icarus-verilog
2. Download [Scansion](http://www.logicpoet.com/scansion/) from here.
3. Clone the repository.
4. $ make simulate will:
* compile design+TB
* simulate the verilog design
5. $ make display will:
* display waveforms.
---
## References
1. [NoCRouter - RTL Router Design in SystemVerilog](https://github.com/agalimberti/NoCRouter)
2. [Router 1X3-RTL Design and Verification](https://www.researchgate.net/publication/329236255_Router_1X3-RTL_Design_and_Verification)
3. [DESIGN OF A 5 PORT ROUTER FOR NOC USING VERILOG](https://www.researchgate.net/publication/338296428_DESIGN_OF_A_5_PORT_ROUTER_FOR_NOC_USING_VERILOG)
#### TODO
- ✅ Add specifications
- ✅ Fifo: Fix output data