https://github.com/yasnakateb/pipelinedarm
💎 A 32-bit ARM Processor Implementation in Verilog HDL
https://github.com/yasnakateb/pipelinedarm
arm arm-pipeline arm-processor cpu icarus-verilog iverilog verilog verilog-hdl
Last synced: 4 months ago
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💎 A 32-bit ARM Processor Implementation in Verilog HDL
- Host: GitHub
- URL: https://github.com/yasnakateb/pipelinedarm
- Owner: yasnakateb
- Created: 2022-02-11T23:35:35.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-03-21T19:33:43.000Z (over 3 years ago)
- Last Synced: 2025-01-20T00:56:21.258Z (5 months ago)
- Topics: arm, arm-pipeline, arm-processor, cpu, icarus-verilog, iverilog, verilog, verilog-hdl
- Language: Verilog
- Homepage:
- Size: 55.7 KB
- Stars: 19
- Watchers: 2
- Forks: 3
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# PipelinedARM
The Arm architecture is a family of reduced instruction set computing (RISC) architectures for computer processors. In this project, a 32-bit pipelined ARM processor is implemented in Verilog HDL.
## The overall architecture
## Implementation
### Stages
ARM pipeline has five stages, with one step per stage:
• IF: Instruction fetch from memory.
• ID: Instruction decode & register read.
• EX: Execute operation or calculate address.
• MEM: Access memory operand.
• WB: Write result back to register.
Each stage takes in data from that buffer, processes it and write into the next buffer. Also note that as an instruction moves down the pipeline from one buffer to the next, its relevant information also moves along with it.
### Instructions
| Instruction Mnemonic | Definition |
|----------------------|---------------------|
| MOV | Move |
| MVN | Move NOT |
| ADD | Add |
| ADC | Add with Carry |
| SUB | Subtract |
| SBC | Subtract with Carry |
| AND | Logical AND |
| ORR | Logical OR |
| EOR | Exclusive OR |
| CMP | Compare |
| TST | Test |
| LDR | Load Register |
| STR | Store Register |
| B | Branch |
## Dependencies
### macOS
This project needs [Icarus-Verilog](http://iverilog.icarus.com) and a VCD viewer.
## Building on macOS
1. Icarus-Verilog can be installed via Homebrew :
$ brew install icarus-verilog
2. Download [Scansion](http://www.logicpoet.com/scansion/) from here.
3. Clone the repository.
4. Run $ make and type MIPS code to see it in binary form in rams_init_file.hex file.
5. $ make simulate will:
* compile design+TB
* simulate the verilog design
6. $ make display will:
* display waveforms.
## Links
1. [ARM Instruction Set](https://profile.iiita.ac.in/bibhas.ghoshal/COA_2021/lecture_slides/arm_inst.pdf)
2. [Introduction to ARM Instructions (azeria labs)](https://azeria-labs.com/arm-instruction-set-part-3/)
#### TODO
- â• Add more instructions