https://github.com/yasnakateb/pipelinedarm

💎 A 32-bit ARM Processor Implementation in Verilog HDL
https://github.com/yasnakateb/pipelinedarm

arm arm-pipeline arm-processor cpu icarus-verilog iverilog verilog verilog-hdl

Last synced: about 2 months ago
JSON representation

💎 A 32-bit ARM Processor Implementation in Verilog HDL

• Host: GitHub
• URL: https://github.com/yasnakateb/pipelinedarm
• Owner: yasnakateb
• Created: 2022-02-11T23:35:35.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-03-21T19:33:43.000Z (almost 3 years ago)
• Last Synced: 2023-03-09T08:11:37.691Z (almost 2 years ago)
• Topics: arm, arm-pipeline, arm-processor, cpu, icarus-verilog, iverilog, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 55.7 KB
• Stars: 5
• Watchers: 3
• Forks: 2
• Open Issues: 0

Awesome Lists containing this project