https://github.com/yasnakateb/sdramcontroller

🛠 A SDRAM controller in Verilog HDL
https://github.com/yasnakateb/sdramcontroller

icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl

Last synced: 4 months ago
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🛠 A SDRAM controller in Verilog HDL

• Host: GitHub
• URL: https://github.com/yasnakateb/sdramcontroller
• Owner: yasnakateb
• Created: 2020-12-28T11:45:24.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2022-03-21T19:40:11.000Z (over 3 years ago)
• Last Synced: 2025-01-20T00:56:21.769Z (5 months ago)
• Topics: icarus-verilog, iverilog, memory-controller, sdram, sdram-controller, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 47.9 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
## Synchronous dynamic random-access memory (SDRAM) controller 

SDRAM is dynamic random access memory (DRAM) with a synchronous interface. It means that SDRAM uses a clock while DRAM does not. The interface has the system bus carrying data between the CPU and the memory controller hub. The memory controller will accept memory requests from the CPU, analyze the requests and dispatch them to the SDRAM in an efficient manner. This SDRAM Controller is simple and only one bank is active at a time.

### View of SDRAM controller

![](assets/view.png)

## Building on macOS

1. Icarus-Verilog can be installed via Homebrew :

   $ brew install icarus-verilog

2. Download [Scansion](http://www.logicpoet.com/scansion/) from here.  

3. Clone the repository.

4. Run $ make  and type MIPS code to see it in binary form in rams_init_file.hex file. 

5. $ make simulate will: 

* compile design+TB

* simulate the verilog design

6. $ make display will: 

*  display waveforms.

## Links 

1. [Design and Verification of SDRAM Controller Based on FPGA](https://www.scirp.org/pdf/jcc_2020070314282156.pdf) 

2. [FPGA VHDL SDRAM Controller](https://dnotq.io/sdram/sdram.html)