https://github.com/yasnakateb/sdramcontroller

🛠 A SDRAM controller in Verilog HDL
https://github.com/yasnakateb/sdramcontroller

icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl

Last synced: about 2 months ago
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🛠 A SDRAM controller in Verilog HDL

• Host: GitHub
• URL: https://github.com/yasnakateb/sdramcontroller
• Owner: yasnakateb
• Created: 2020-12-28T11:45:24.000Z (about 4 years ago)
• Default Branch: main
• Last Pushed: 2022-03-21T19:40:11.000Z (almost 3 years ago)
• Last Synced: 2023-03-09T08:11:37.748Z (almost 2 years ago)
• Topics: icarus-verilog, iverilog, memory-controller, sdram, sdram-controller, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 47.9 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0

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