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https://github.com/yehiashaarawy/mips-architecture
MIPS Processor implementation of single cycle
https://github.com/yehiashaarawy/mips-architecture
vhdl
Last synced: 26 days ago
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MIPS Processor implementation of single cycle
- Host: GitHub
- URL: https://github.com/yehiashaarawy/mips-architecture
- Owner: YehiaShaarawy
- Created: 2023-06-06T01:31:02.000Z (over 1 year ago)
- Default Branch: master
- Last Pushed: 2023-06-06T01:44:43.000Z (over 1 year ago)
- Last Synced: 2024-11-15T23:23:40.818Z (about 2 months ago)
- Topics: vhdl
- Language: C
- Homepage:
- Size: 746 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# MIPS-Architecture
MIPS Processor implementation of single cycle using Xilinx ISE and VHDL.
## Tech Stack
- VHDL
## Green Sheet for MIPS Architecture
## Single Cycle MIPS Architecture
## Some used parameters
### Memory File
- Memory[0]= 0x”ABCDEF00”
- Memory[1]= 0x”75746572”
- Memory[2]= 0x”20417263”
- Memory[3]= 0x”68697465”
- Memory[4] = 0x”12345678”
- Memory[5]= 0x”7F7F6D6D”
- Memory[6]= 0x”00000000”
- Memory[7]= 0x”78786A6A”
- Memory[8]= 0x”00000001”
### Register File
- $a0 = 5
- $a1 = 7
### Instructions
- add $v0, $a0, $a1
- sw $v0, 8($zero)
- lw $a2, 8($zero)
- beq $v0, $a2, Good_Processor
- slt $s1, $v0, $a2
- Good_Processor: sub $s1, $a1, $a0
## Output Simulation
## Report
[MIPS Project Report - Yehia Sharawy 20100519 .pdf](https://github.com/YehiaSharawy/MIPS-Architecture/files/11659017/MIPS.Project.Report.-.Yehia.Sharawy.20100519.pdf)