https://github.com/yehiasharawy/mips-architecture

Implementation of a MIPS processor architecture for a single cycle using VHDL
https://github.com/yehiasharawy/mips-architecture

mips mips-architecture vhdl xilinx-ise

Last synced: 6 days ago
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Implementation of a MIPS processor architecture for a single cycle using VHDL

• Host: GitHub
• URL: https://github.com/yehiasharawy/mips-architecture
• Owner: YehiaSharawy
• Created: 2023-06-06T01:31:02.000Z (over 1 year ago)
• Default Branch: master
• Last Pushed: 2025-02-01T17:31:39.000Z (13 days ago)
• Last Synced: 2025-02-08T19:45:52.210Z (6 days ago)
• Topics: mips, mips-architecture, vhdl, xilinx-ise
• Language: C
• Homepage:
• Size: 748 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# MIPS Architecture

Implementing a MIPS processor architecture of a single cycle using Xilinx ISE tool and VHDL as a programming language.

 

# Green Sheet for MIPS Architecture



# Single Cycle MIPS Architecture



#Parameters used to run the architecture

### Memory File

- Memory[0]= 0x”ABCDEF00”

- Memory[1]= 0x”75746572”

- Memory[2]= 0x”20417263”

- Memory[3]= 0x”68697465”

- Memory[4] = 0x”12345678”

- Memory[5]= 0x”7F7F6D6D”

- Memory[6]= 0x”00000000”

- Memory[7]= 0x”78786A6A”

- Memory[8]= 0x”00000001”

### Register File

- $a0 = 5

- $a1 = 7

### Instructions

- add $v0, $a0, $a1

- sw $v0, 8($zero)

- lw $a2, 8($zero)

- beq $v0, $a2, Good_Processor

- slt $s1, $v0, $a2

- Good_Processor: sub $s1, $a1, $a0

# Output Simulation

![2](https://github.com/YehiaSharawy/MIPS-Architecture/assets/65984199/57ed4b1f-d5b3-435f-a53e-369ba3051946)

# Documentation

[MIPS Documentation.pdf](https://github.com/YehiaSharawy/MIPS-Architecture/files/11659017/MIPS.Project.Report.-.Yehia.Sharawy.20100519.pdf)