https://github.com/yixin0829/ece241-fpga-final-project
FPGA project using DE1-SoC board that can process images into different filter effects
https://github.com/yixin0829/ece241-fpga-final-project
de1-soc verilog
Last synced: 6 months ago
JSON representation
FPGA project using DE1-SoC board that can process images into different filter effects
- Host: GitHub
- URL: https://github.com/yixin0829/ece241-fpga-final-project
- Owner: yixin0829
- Created: 2019-11-22T20:38:34.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2020-01-01T21:23:43.000Z (almost 6 years ago)
- Last Synced: 2024-04-14T03:06:14.166Z (over 1 year ago)
- Topics: de1-soc, verilog
- Language: Verilog
- Homepage:
- Size: 98.4 MB
- Stars: 0
- Watchers: 1
- Forks: 1
- Open Issues: 0