https://github.com/ysayaovong/multiplexers-decoders-and-the-arithmetic-logic-unit-alu

https://github.com/ysayaovong/multiplexers-decoders-and-the-arithmetic-logic-unit-alu

Last synced: about 1 month ago
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• Host: GitHub
• URL: https://github.com/ysayaovong/multiplexers-decoders-and-the-arithmetic-logic-unit-alu
• Owner: YSayaovong
• Created: 2024-08-02T12:40:06.000Z (5 months ago)
• Default Branch: main
• Last Pushed: 2024-09-11T16:37:17.000Z (4 months ago)
• Last Synced: 2024-09-12T01:51:11.768Z (4 months ago)
• Language: HTML
• Size: 3.55 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Multiplexers, Decoders, and the Arithmetic Logic Unit (ALU)

This repository contains exercises and implementations of multiplexers, decoders, and an Arithmetic Logic Unit (ALU). It covers how these components are used in digital systems.

### Features:

- Implementations of multiplexers and decoders.

- ALU design and functionality in digital circuits.

This project helps users understand the role of these key components in digital computing.