https://github.com/yugr/parmatch

A simple script for finding unbound parameters in Verilog module instantiations.
https://github.com/yugr/parmatch

static-analysis static-analyzer verilog

Last synced: about 2 months ago
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A simple script for finding unbound parameters in Verilog module instantiations.

• Host: GitHub
• URL: https://github.com/yugr/parmatch
• Owner: yugr
• License: mit
• Created: 2016-10-14T06:43:37.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2016-10-28T06:19:51.000Z (over 8 years ago)
• Last Synced: 2024-11-07T04:47:23.383Z (3 months ago)
• Topics: static-analysis, static-analyzer, verilog
• Language: Perl
• Size: 22.5 KB
• Stars: 3
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE.txt

Awesome Lists containing this project

README

        
Parmatch is a super-primitive script for finding unbound parameters

in Verilog module instantiations (which may be cause of bugs and

are prohibited by some coding conventions).