https://github.com/yugr/primogen

A toy prime number generator in Verilog
https://github.com/yugr/primogen

fpga ice40 lattice

Last synced: about 6 hours ago
JSON representation

A toy prime number generator in Verilog

• Host: GitHub
• URL: https://github.com/yugr/primogen
• Owner: yugr
• License: mit
• Created: 2016-07-09T20:35:58.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2016-10-09T19:20:23.000Z (about 8 years ago)
• Last Synced: 2023-03-08T22:25:47.352Z (over 1 year ago)
• Topics: fpga, ice40, lattice
• Language: Verilog
• Size: 92.8 KB
• Stars: 7
• Watchers: 3
• Forks: 1
• Open Issues: 0

Awesome Lists containing this project