https://github.com/yvesemmanuel/introduction_verilog

digital systems
https://github.com/yvesemmanuel/introduction_verilog

digital-systems verilog verilog-components verilog-project

Last synced: 3 months ago
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digital systems

• Host: GitHub
• URL: https://github.com/yvesemmanuel/introduction_verilog
• Owner: yvesemmanuel
• Created: 2021-08-11T04:11:57.000Z (almost 4 years ago)
• Default Branch: master
• Last Pushed: 2021-08-26T21:08:37.000Z (almost 4 years ago)
• Last Synced: 2025-01-16T21:12:31.876Z (5 months ago)
• Topics: digital-systems, verilog, verilog-components, verilog-project
• Language: Verilog
• Homepage:
• Size: 202 KB
• Stars: 2
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# Verilog Project - combinational circuits

# [Tri-state buffer](https://github.com/yvesemmanuel/verilog_project/blob/master/Q1/buffer.v)

![buffer](images/Q1.jpg)

# [Combinational circuit with delay](https://github.com/yvesemmanuel/verilog_project/blob/master/Q2/combinational_delay.v)

![circuit](images/Q2.png)

# [Conditional circuit](https://github.com/yvesemmanuel/verilog_project/blob/master/Q2/combinational_delay.v)

![conditional](images/Q3.png)

# [4 & 8 bit comparator](https://github.com/yvesemmanuel/verilog_project/tree/master/Q5)

![comparators](images/Q5.png)