https://github.com/z1skgr/reconf-computing__hls
High Level synthesis of data transfer in Vivado, Vivado HLS
https://github.com/z1skgr/reconf-computing__hls
data-structures data-system embedded-c embedded-systems fifo-queue high-level-synthesis hls simulation vivado vivado-hls xilinx xilinx-vivado xilinx-zynq
Last synced: about 1 month ago
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High Level synthesis of data transfer in Vivado, Vivado HLS
- Host: GitHub
- URL: https://github.com/z1skgr/reconf-computing__hls
- Owner: z1skgr
- Created: 2022-03-26T12:30:20.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2022-05-16T20:39:59.000Z (almost 3 years ago)
- Last Synced: 2025-01-23T09:11:29.703Z (3 months ago)
- Topics: data-structures, data-system, embedded-c, embedded-systems, fifo-queue, high-level-synthesis, hls, simulation, vivado, vivado-hls, xilinx, xilinx-vivado, xilinx-zynq
- Language: C++
- Homepage:
- Size: 53.2 MB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 11
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Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# reconfigurable Computing
> Designing Protocol Processing Systems with Vivado High-Level Synthesis
## Parts
* [64-FIFO Implementantion 32 bits words](1/README.md)
* [Data flow-system implementation](2/README.md)
* [64-FIFO and Data flow-system in a integrated design](3/README.md)
## Setup
Vivado 2017.4 and Vivado HLS 2017.4 Xilinx®
To run the project:
Install [Vivado 2017.4 HL design edition (full version)](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html)
* SoC -> Zynq 7000
## Acknowledgement
This project was created for the requirements of the lesson Reconfigurable Programming/Computing.
[^1]: If IP is not available, means you did not select the SoC Zync 7000 device. To add it, you will do through the Vivado project: Help ? Add design tools. Enter user name/password, and on the next screen select Upgrade installation to Vivado HL Design Edition. Then select Devices -> Production Devices -> SoCs -> Zynq 7000