https://github.com/z1skgr/tomasulo-based-processor
TOMASULO processor in VHDL implementation
https://github.com/z1skgr/tomasulo-based-processor
computer-architecture fpga pipeline processor simulation tomasulo vhdl xilinx-ise
Last synced: about 1 month ago
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TOMASULO processor in VHDL implementation
- Host: GitHub
- URL: https://github.com/z1skgr/tomasulo-based-processor
- Owner: z1skgr
- Created: 2020-10-30T20:27:00.000Z (almost 5 years ago)
- Default Branch: main
- Last Pushed: 2022-05-16T20:35:24.000Z (over 3 years ago)
- Last Synced: 2025-03-16T22:46:26.334Z (7 months ago)
- Topics: computer-architecture, fpga, pipeline, processor, simulation, tomasulo, vhdl, xilinx-ise
- Language: VHDL
- Homepage:
- Size: 14.7 MB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 4
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Metadata Files:
- Readme: README.md
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README
# Dynamic/PipelineProcessor
> Simple Tomasulo based processor back-end using VHDL.
## Parts
* [Tomasulo algorithm](1/README.md)
* [Tomasulo + Reorder Buffer + Ld/St Queue](3/readme3.md)
## Setup
Xilinx ISE® design suite 13.7 and above
To run the project
1. Install Xilinx suite from https://www.xilinx.com/downloadNav/vivado-design-tools/archive-ise.html
2. Clone code from [git](https://github.com/z1skgr/Tomasulo-BASED-processor)
3. File > Import > Existing Projects into Workspace > Locate project
* Copy projects into workspace if you do want to copy the project files to your current workspace location.
To run the simulation (.wcfg)
1. Find simulation files in hierarchy
* Import them if they do not appear
2. Simulate behavioral model
3. Check system behavior based on scenarios (different input signal)
## Acknowledgements
* This project was created for the requirements of the lesson Computer Architecture