https://github.com/z4yx/NaiveMIPS-HDL

Naïve MIPS32 SoC implementation
https://github.com/z4yx/NaiveMIPS-HDL

cpu mips verilog

Last synced: 3 months ago
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Naïve MIPS32 SoC implementation

• Host: GitHub
• URL: https://github.com/z4yx/NaiveMIPS-HDL
• Owner: z4yx
• Created: 2017-11-14T05:17:43.000Z (about 7 years ago)
• Default Branch: brd-NSCSCC
• Last Pushed: 2020-06-23T11:28:08.000Z (over 4 years ago)
• Last Synced: 2024-10-15T17:50:46.923Z (4 months ago)
• Topics: cpu, mips, verilog
• Language: Verilog
• Homepage:
• Size: 298 MB
• Stars: 113
• Watchers: 7
• Forks: 35
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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