https://github.com/z4yx/NaiveMIPS-HDL
Naïve MIPS32 SoC implementation
https://github.com/z4yx/NaiveMIPS-HDL
cpu mips verilog
Last synced: about 1 year ago
JSON representation
Naïve MIPS32 SoC implementation
- Host: GitHub
- URL: https://github.com/z4yx/NaiveMIPS-HDL
- Owner: z4yx
- Created: 2017-11-14T05:17:43.000Z (over 8 years ago)
- Default Branch: brd-NSCSCC
- Last Pushed: 2020-06-23T11:28:08.000Z (almost 6 years ago)
- Last Synced: 2025-04-09T23:50:52.408Z (about 1 year ago)
- Topics: cpu, mips, verilog
- Language: Verilog
- Homepage:
- Size: 298 MB
- Stars: 113
- Watchers: 6
- Forks: 35
- Open Issues: 0
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Metadata Files:
- Readme: README.md